1. Field of the Invention
The present invention relates to a decoding circuit, particularly to a configurable hierarchical comma-free Reed-Solomon decoding circuit.
2. Description of the Related Art
In a WCDMA (Wideband Code Division Multiple Access) communication system, the comma-free Reed-Solomon (CFRS) code is decoded to define the frame boundary and the scrambling code group in the second stage of the synchronization process. The CFRS code has the features of the comma-free code and the Reed-Solomon code. The comma-free code is characterized in that none combination of successive members can form a new comma-free code. Further, the comma-free code has the capabilities of debug and synchronization. The WCDMA system relies on the synchronization capability of the comma-free code in synchronizing the frame. In common applications, the comma-free code is usually decoded with a simple continuous correlator. However, the comma-free code is not continuously but intermittently transmitted in a WCDMA system. Therefore, common comma-free decoders cannot apply to the synchronization process of the WCDMA system. There are not many existing papers concerning the comma-free Reed-Solomon decoding circuits for the WCDMA system. Refer to FIG. 1 for the most recent prior art of the CFRS decoding circuit for the WCDMA system. The decoding circuit is based on a systolic array architecture and can quickly perform decoding to meet the requirements of various synchronization algorithms. The decoding circuit comprises an input-signal generator (such as that shown in FIG. 2), 64×15 pieces of processing elements (such as that shown in FIG. 3), and 64×1 pieces of boundary processing elements (such as that shown in FIG. 4). During decoding, the CFRS code is loaded into the input-signal generator, and the input-signal generator sequentially generates fifteen combinations of cyclic shifts. The cyclic shifts are input into the 64×15 processing element array in an oblique manner. The processing element array compares the fifteen combinations of cyclic shifts with sixty-four sets of pre-stored codes. Each row of the processing element array performs the comparison for one set of probable CFRS code. The boundary processing element of the same row finds out the most probable cyclic shift for the result output by the row. Then, the most probable cyclic shifts for the results of all the rows are checked vertically top down to find out the maximum cyclic shift among the rows, and the lowest boundary processing element outputs the result of decoding. Refer to FIG. 5. The prior art also proposes a folding technology to reduce the size of the systolic array from 64×15 to (32, 16, 8, 4, 2, or 1)×15, whereby the area of the systolic array is decreased. Similarly, the size of the boundary array is reduced from 64×1 to (32, 16, 8, 4, 2, or 1)×1. However, as shown in FIG. 6, the restricted decoding rate thereof is still hard to satisfy designers.
To overcome the abovementioned problems, the present invention proposes a configurable hierarchical CFRS decoding circuit, which is able to determine the frame boundary and the scrambling code group after the fifteen secondary synchronization codes have been sequentially attained in the second stage of the three-stage code synchronization of a WCDMA system. Based on a hierarchical parallel architecture, the present invention appropriately controls the path of data flow to achieve a configurable decoding circuit, whereby the user can configure the speed and power consumption of the decoding circuit to satisfy various applications.